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| rev 1.0 9/14 copyright ? 2014 by silicon laboratories em359x em359x high-performance, integrated zigb ee/802.15.4 system-on-chip family complete system-on-chip - 32-bit arm? cortex -m3 processor - 2.4 ghz ieee 802.15.4-2003 transceiver & lower mac - 256 or 512 kb flash, with optional read protection - 32 or 64 kb ram memory - aes128 encryption accelerator - flexible adc, uart/spi/twi serial communications, and general purpose timers - optional usb serial communications - 32 highly configurable gpios with schmitt trigger inputs industry-leading arm? cortex -m3 processor - leading 32-bit processing performance - highly efficient thumb-2 instruction set - operation at 6, 12, or 24 mhz - flexible nested vectored interrupt controller low power consumption, advanced management - rx current (w/ cpu): 27 ma - tx current (w/ cpu, +3 dbm tx): 31 ma - low deep sleep current, with retained ram and gpio: 1.0 ? a without/1.25 ? a with sleep timer - low-frequency internal rc oscillator for low-power sleep timing - high-frequency internal rc oscillator for fast (110 s) processor start-up from sleep exceptional rf performance - normal mode link budget up to 103 db; configurable up to 110 db - ?100 dbm normal rx sensit ivity; configurable to ? ?102 dbm (1% per, 20 byte packet) - +3 db normal mode output power; configurable up to +8 dbm - robust wi-fi and bluetooth coexistence innovative network and processor debug - packet trace port for non-intrusive packet trace with ember development tools - serial wire/j tag interface - standard arm debug capabilities: flash patch & break - point; data watchpoint & trace; instrumentation trace macrocell application flexibility - single voltage operation: 2.1?3.6 v with internal 1.8 and 1.25 v regulators - optional 32.768 khz crystal for higher timer accuracy - low external component count with single 24 mhz ? crystal - support for external power amplifier - 8x8 mm 56-pin qfn package adc rf_p,n program flash 256/512 kb data ram 32/64 kb hf ? crystal ? osc lf ? crystal ? osc general purpose adc serial wire and jtag debug internal lf rc-osc gpio multiplexor switch chip manager 1.8v ? regulator bias 2 nd level interrupt controller rf_tx_alt_p,n osca oscb pa[7:0], pb[7:0], pc[7:0], pd[4:1], pe[3:0] encryption ? acclerator if always powered domain arm ? cortex tm -m3 cpu with nvic and mpu vreg_out watchdog pa ? select lna pa pa dac mac + baseband sleep timer por nreset general ? purpose ? timers gpio registers uart/spi/ twi synth internal hf rc-osc tx_active calibration adc packet ? trace cpu debug tpiu/ itm/fpb/dwt/ etm 1.25v ? regulator vdd_core usb device swclk, ? jtck ?
em359x 2 rev 1.0 general description the ember em359x is a fully integrated system-on-chip th at integrates a 2.4 ghz, ieee 802.15.4- 2003-compliant transceiver, 32-bit arm ? cortex tm -m3 microprocessor, flash and ram memory, and peripherals of use to designers of zigbee-based systems. the transceiver uses an effi cient architecture t hat exceeds th e dynamic range requiremen ts imposed by the ieee 802.15.4-2003 standard by over 15 db. the integrated rece ive channel filteri ng allows for robust co-existence with other communication standards in the 2.4 ghz spectrum, such as ieee 8 02.11-2007 and bluetoot h. the integrated regulator, vco, loop filter, and po wer amplifier keep the external component count low. an optional high performance radio mode (boost mode) is so ftware-selectable to boost dynamic range. the integrated 32-bit arm ? cortex tm -m3 microprocessor is highly optimized for high performance, low power consumption, and efficient memory ut ilization. including an inte grated mpu, it supports two different modes of operation?privileged mode and user mo de. this architecture could allow fo r separation of the networking stack from the application code, and prevents unwanted modi fication of restricted area s of memory and registers resulting in increased stability and reliability of deployed solutions. the em359x has either 256 or 512 kb of embedded flash me mory and either 32 or 64 kb of integrated ram for data and program storage. the ember software for the em35 9x employs an effective we ar-leveling algorithm that optimizes the lifetime of the embedded flash. to maintain the strict timi ng requirements impo sed by the zigbee and ieee 802.15 .4-2003 standards, the em359x integrates a number of mac functions, aes128 encrypti on accelerator, and automatic crc handling into the hardware. the mac hardware handles automatic ack transmission and reception, automatic backoff delay, and clear channel assessment for transmission, as well as automatic filtering of received packets. the ember packet trace interface is also integrated with the mac, allowing complete, non-intrusive capture of all packets to and from the em359x with ember development tools. the em359x offers a number of advanced power management features that enable long battery life. a high- frequency internal rc oscillator allows the processor core to begin code execution quickly upon waking. various deep sleep modes are available with less than 2 a powe r consumption while retainin g ram contents. to support user-defined applications, on-chip peripherals include op tional usb, uart, spi, twi, adc, and general-purpose timers, as well as up to 32 gpios. additionally, an inte grated voltage regulator, power-on-reset circuit, and sleep timer are available. finally, the em359x utilizes standard serial wire and jtag interfaces fo r powerful software debugging and programming of the arm cortex tm -m3 core. the em359x integrates the standard arm ? system debug components: flash patch and breakpoint (fpb), data watchpoint and trace (dwt), and instrumentation trace macrocell (itm) as well as the advanced embedded trace macrocell (etm). target applications for the em359x include: ?? smart energy ?? building automation and control ?? home automation and control ?? security and monitoring ?? general zigbee wireless sensor networking this technical data sheet details the em359x features available to customers using it with ember software. em359x rev 1.0 3 table of contents 1. related documents and conventions . ................. ................ ................. ................ ............5 1.1. related documents............ ................. ................ ................ ................. .............. ............5 1.1.1. ember em359x reference manual.... .............. .............. .............. .............. ............5 1.1.2. zigbee specification ....... ................ ................. .............. .............. .............. ............5 1.1.3. zigbee pro stack profile ... .............. .............. .............. .............. .............. ............5 1.1.4. zigbee stack profile ....... ................ ................. .............. .............. .............. ............5 1.1.5. bluetooth core specification ...... ................ ................ ................. .............. ............5 1.1.6. ieee 802.15.4-2003 .............. ................ ................. ................ ................. ..............5 1.1.7. ieee 802.11g............. ................. ................ ................ ................. .............. ............5 1.1.8. usb 2.0 specification ..... ................ ................. .............. .............. .............. ............5 1.1.9. arm? cortex?-m3 reference m anual ................. ................ ................. ..............5 1.2. conventions .............. ................ ................. .............. .............. .............. .............. ............6 2. typical connection diagrams ............ ................ ................. ................ ................. ..............9 3. electrical specifications................. ................. .............. .............. .............. .............. .......... 13 3.1. absolute maximum ratings... ................ ................ ................. .............. .............. ..........13 3.2. recommended operating conditions .... ............... ................. .............. .............. .......... 13 3.3. environmental characteristics........ ................ ................. ................ ................. ............ 14 3.4. dc electrical char acteristics............... ................ ................ ................. .............. .......... 14 3.5. digital i/o specifications .. ................ ................. ................ ................. ................ .......... 19 3.6. non-rf system electrical characteristics .......... ................ ................. .............. .......... 20 3.7. rf electrical characteristics ........ .............. .............. .............. .............. .............. .......... 21 3.7.1. receive............. ................ ................. .............. .............. .............. .............. .......... 21 3.7.2. transmit................. ................ ................ ................. ................ ................. ............24 3.7.3. synthesizer .............. ................ ................. ................ ................. ................ .......... 26 4. em359x system overview.......... ................ ................ ................. .............. .............. ..........27 4.1. microprocessor and memory............ ................. ................ ................. ................ .......... 28 4.1.1. arm? cortex?-m3 microprocessor . .............. .............. .............. .............. .......... 28 4.1.2. embedded memory ............. .............. .............. .............. .............. .............. .......... 29 4.2. interrupt system ............. ................ ................ ................. ................ ................. ............ 29 4.2.1. nested vectored interrupt contro ller (nvic) ............ ................. ................ ..........29 4.2.2. event manager ............... ................ ................. .............. .............. .............. .......... 29 4.2.3. memory protection unit .......... .............. .............. .............. .............. ..........29 4.3. radio module ............ ................ ................. .............. .............. .............. .............. ..........29 4.3.1. receive (rx) path......... ................ ................ ................. .............. .............. .......... 29 4.3.2. transmit (tx) path ................... ................. ................ ................. ................ .......... 30 4.3.3. integrated mac module....... .............. .............. .............. .............. .............. .......... 30 4.3.4. packet trace interface (pti)....... ................ ................ ................. .............. .......... 30 4.3.5. random number generator .............. .............. .............. .............. .............. .......... 30 4.4. system modules............... ................ ................. ................ ................. ................ .......... 30 4.4.1. power domains ............... ................ ................. .............. .............. .............. .......... 30 4.4.2. resets............. ................ ................ ................. .............. .............. .............. .......... 31 4.4.3. clocks ................. ................. .............. .............. .............. .............. .............. .......... 31 4.4.4. system timers......... ................ ................. ................ ................. ................ .......... 31 4.4.5. power management............. .............. .............. .............. .............. .............. .......... 31 em359x 4 rev 1.0 4.5. integrated voltage regulator ........... ................. ................ ................. ................ .......... 32 4.6. peripherals .............. ................ ................ .............. .............. ............... .............. ............ 3 2 4.6.1. gpio .................... ................ ................ ................. ................ ................. ............ 32 4.6.2. serial controllers .......... ................ ................ ................. .............. .............. ..........32 4.6.3. usb ................. ................. .............. .............. .............. .............. .............. .......... 33 4.6.4. general purpose timers............. ................ ................ ................. .............. .......... 33 4.6.5. analog-to-digital converter (adc ) .................. .............. .............. .............. .......... 34 4.7. debugging ................. ................ ................. .............. .............. .............. .............. .......... 34 4.7.1. trace port interface unit (tpiu) ................... ................. .............. .............. .......... 34 4.7.2. instrumentation trace macrocell (itm)............ .............. .............. .............. .......... 34 4.7.3. embedded trace macrocell (etm).... .............. .............. .............. .............. .......... 34 4.7.4. data watchpoint and trace (dwt ).............. ................ ................. ............ 34 4.7.5. flash patch and breakpoint (fpb) .... .............. .............. .............. .............. .......... 35 4.7.6. serial wire and jtag (swj) inte rface ............ .............. .............. .............. .......... 35 5. ordering information ........... ................ ................ ................. ................ ................. ............ 36 6. pin assignments............... ................. ................ ................ ................. ................ ............... 37 6.1. packaging................ ................ ................ .............. .............. ............... .............. ............ 5 3 6.2. part marking ............ ................ ................ ................. .............. .............. .............. .......... 57 document change list ........ ................ .............. .............. .............. ............... .............. ............ 58 contact information ........... ................ ................ ................. ................ ................. ............... .... 59 em359x rev 1.0 5 1. related documents and conventions 1.1. related documents this data sheet accompanie s several documents to provide the complete description of the ember em359x devices. 1.1.1. ember em359x reference manual the silicon laboratories em ber em359x reference ma nual provides the detailed descr iption for each peripheral on the em359x devices. 1.1.2. zigbee specification the core zigbee specification (document 053474) defines zigbee's smart, cost-effective and energy-efficient mesh network. it can be do wnloaded from the zigbee website (www.zig bee.org). zigbee allia nce membership is required. 1.1.3. zigbee pro stack profile the zigbee pro stack profile specification (document 07 4855) is optimized for low power consumption and to support large networks with thousands of devices. it can be downloaded from the zigb ee website (111.zigbee.org). zigbee alliance membership is required. 1.1.4. zigbee stack profile the zigbee stack profile specificatio n (document 064321) is designed to support smaller networks with hundreds of devices in a single network. it can be downloaded from the zigbee we bsite (111.zigbee.org). zigbee alliance membership is required. 1.1.5. bluetooth core specification the bluetooth specification is the glo bal short-range wireless standard enabling connectivity for a broad range of electronic devices. version 2.1 + edr (enhanced data rate) can be found here: http://www.bluetooth .org/docman/handlers/downl oaddoc.ashx?doc_id=241363 1.1.6. ieee 802.15.4-2003 this standard defines the protocol and compatible inte rconnection for data communication devices using low data rate, low power and low complexity, short-range radio frequency (rf) transmissions in a wireless personal area network (wpan). it can be found here: ieee 802.15.4-2003 ( http://standards.ieee.org/getieee802/download/802.15.4-2003.pdf ) 1.1.7. ieee 802.11g this version provides changes and additions to support the further higher data rate extension for operation in the 2.4 ghz band. it can be found here: http://standards.ieee.org/getieee802/download/802.11g-2003.pdf 1.1.8. usb 2.0 specification the universal serial bus revision 2.0 specification provides the technical details to understand usb requirements and design usb compatible products. the main specificat ion (usb_20.pdf) is part of the zipfile found here: http://www.usb.org/developers/docs/usb_20_101111.zip 1.1.9. arm ? cortex?-m3 reference manual arm-specific features like the nested vector interrupt controller are described in the arm ? cortex?-m3 reference documentation. the online reference manual can be found here: http://infocenter.arm.com/help/ topic/com.arm.doc.subset.cor texm.m3/index.html#cortexm3 em359x 6 rev 1.0 1.2. conventions abbreviations and acronyms used in this data sheet are explained in ta b l e 1.1 table 1.1. acronyms and abbreviations acronym/abbreviation meaning ack acknowledgement adc analog to digital converter aes advanced encryption standard agc automatic ga in control ahb advanced high speed bus apb advanced peripheral bus cbc-mac cipher block chaining?message authentication code cca clear channel assessment ccm counter with cbc-mac mode for aes encryption ccm* improved counter with cbc -mac mode for aes encryption cib customer information block clk1k 1 khz clock clk32k 32.768 khz crystal clock cpu central processing unit crc cyclic redundancy check csma-ca carrier sense multiple access-collision avoidance ctr counter mode cts clear to send dnl differential non-linearity dma direct memory access dwt data watchpoint and trace eeprom electrically erasable programmable read only memory em event manager enob effective number of bits esd electro static discharge esr equivalent series resistance etr external trigger input fclk arm ? cortex tm -m3 cpu clock fib fixed information block fifo first-in, first-out em359x rev 1.0 7 fpb flash patch and breakpoint gpio general purpose i/o (pins) hf high frequency i 2 c inter-integr ated circuit ide integrated development environment if intermediate frequency ieee institute of electrical and electronics engineers inl integral non-linearity itm instrumentation trace macrocell jtag joint test action group lf low frequency lna low noise amplifier lqi link quality indicator lsb least significant bit mac medium access control mfb main flash block miso master in, slave out mos metal oxide semiconductor (p-channel or n-channel) mosi master out, slave in mpu memory protection unit msb most significant bit msl moisture sensitivity level nack negative acknowledge nist national institute of standards and technology nmi non-maskable interrupt nvic nested vectored interrupt controller opm one-pulse mode o-qpsk offset-quadrature phase shift keying osc24m high frequency crystal oscillator osc32k low-frequency 32.768 khz oscillator oschf high-frequency internal rc oscillator oscrc low-frequency rc oscillator pa power amplifier table 1.1. acronyms and abbreviations em359x 8 rev 1.0 pclk peripheral clock per packet error rate phy physical layer pll phase-locked loop por power-on-reset prng pseudo random number generator psd power spectral density pti packet trace interface pwm pulse width modulation qfn quad flat pack ram random access memory rc resistive/capacitive rf radio frequency rms root mean square rohs restriction of hazardous substances rssi receive signal strength indicator rts request to send rx receive sysclk system clock sdfr spurious free dynamic range sfd start frame delimiter sinad signal-to-noise and distortion ratio spi serial peripheral interface swj serial wire and jtag interface thd total harmonic distortion trng true random number generator twi two wire serial interface tx transmit uart universal asynchronous receiver/transmitter uev update event usb universal serial bus vco voltage controlled oscillator table 1.1. acronyms and abbreviations em359x rev 1.0 9 2. typical connection diagrams figure 2.1 illustrates the typical application circuit. note: the circuit shown in figure 2.1 is for example purposes only. for a comple te reference design, please download one of the latest ember hardware reference designs from the silicon labs website ( www.silabs.com/zigbee-support ). the balun provides an impedance transformation from the antenna to the em359x for both tx and rx modes. l4, along with the pcb trace parasitics and the ceramic balun impedence, provide the optimal rf path for maximum transmit power and receive sensitivity for th e em359x system. the harmonic filter (l5, l6, c7, c8 and c9) provides additional suppression of the second harmonic, which increases the margin over the fcc limit. the 24 mhz crystal, y2, with loading capacitors is requi red and provides the high-f requency crystal oscillator source for the em359x?s main system clock. t he optional 32.768 khz crystal, y1, with loading capacitors generates a highly accurate lo w-frequency crystal oscillator for use with peri pherals, but it is not mandatory as the low-frequency internal rc oscillator can be used. loading capacitance and esr (c3 and r3) provides proper loading for the internal 1.8 v regulator. loading capacitance c4 provides proper loading for the inte rnal 1.25 v regulator, no esr is required because it is contained within the chip. resistor r7 reduces the operating voltage of the flash memory. this reduces current consumption and improves sensitivity by 1 db when compared to not using it. various decoupling capacitors are required, these should be placed as close to th eir corresponding pins as possible. for values and locations see on e of the silicon labs reference designs. an antenna impedance matched to 50 ? is required. em359x 10 rev 1.0 figure 2.1. typical application circuit r7 c3 nreset pc5 pa2 pa1 pa0 pb4 pb3 pa7 pc7 pc6 pa3 pa4 pa5 pa6 pb1 pb2 jclk pc2 pc3 pc4 pc1 pc0 pb7 pb6 pb5 r3 vbrd c4 vbrd pc0 pc4 pa4 pc2 pc3 jclk nreset pa5 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 10 10 1 2 3 4 5 6 7 8 9 1 0 j2 vcc 8 nhold 7 sclk 6 si/sio0 5 ncs 1 so/sio1 2 nwp 3 gnd 4 u3 r9 r8 vbrd r11 pb7 3 1 2 q1 pb4 pb2 pb3 pb1 r10 1 2 y1 c6 c5 pc6 pc7 unbal 1 dc 2 bal-1 3 bal-2 4 gnd 5 nc 6 bln1 l4 c7 l5 l6 c8 c9 1v25_core 1v8 pe2 pe3 pb0 pd3 pd2 pd1 pd4 pe0 pe1 vdd_24mhz 2 vdd_vco 3 rf_p 4 rf_n 5 vdd_rf 6 rf_tx_alt_p 7 rf_tx_alt_n 8 vdd_if 9 nc 10 vdd_padsa 11 pc5 12 nreset 13 pc6 14 pc7 15 vreg_out 16 vdd_pads_0 17 vdd_core_0 18 pa7 19 pb3 23 pb4 24 pa0 25 pa1 26 vdd_pads_1 27 pa2 28 pa3 29 pa4 30 pa5 31 vdd_pads_2 35 pa6 36 pb1 37 pb2 38 jtck 39 pc2 40 pc3 41 pc4 42 pb0 43 vdd_pads_3 44 pc1 45 vdd_mem 46 pc0 47 pb7 48 pb6 51 pb5 52 vdd_core_1 53 vcc_pre 54 vdd_synth 55 oscb 56 osca 1 gnd 57 em359x pd1 20 pd2 21 pd3 22 pd4 32 pe0 33 pe1 34 pe2 49 pe3 50 u2 em359x optional 32khz programming/debug interface (optionally route to test points) optional serial flash l2 l1 at1 l3 antenna interface harmonic filter ceramic balun oscb osca 1 2 y2 c10 c11 c15 r4 r2 r1 r6 r5 c13 pa0 pa1 pa2 pa3 c12 vcc 1 d- 2 d+ 3 nc 4 gnd 5 6 7 8 9 j1 optional usb (shown as bus-powered configuration) in 3 gnd 1 out 2 u1 c2 c1 vbrd vbus fb1 d2 tvs d3 tvs d1 tvs esd protection diodes c14 r1/r2 installed for self-powered configuration only (vbus sense) em359x rev 1.0 11 table 2.1. bill of materials for figure 2.1 item qty reference description manufacturer 1 1 ant1 antenna, em359x 12 rev 1.0 27 1 u2 em359x, zigbee/802.15.4 rf transceiver, arm cortex-m3, 32 or 64 kb ram, 256 or 512 kb flash, 56-qfn EM3591-rtr/em3592-rtr/ em3595-rtr/em3596-rtr/ em3597-rtr/em3598-rtr 28 1 u3 ic - programmable memory - blank, serial flash, 8m (256k x 32), 2.7 v - 3.6 v, - 40 to 85 oc, 8-soic (0.154", 3.90mm width) winbond w25q80bvsnig 29 1 y1 crystal, 32.768 khz, 20 ppm initial tol - erance at +25oc, 12.5 pf abracon abs07-32.768khz-t 30 1 y2 oscillator, crystal, 24.000 mhz, 18 pf load, 10 ppm tolerance, 25 ppm sta - bility, -40 to 85 oc, at49 abracon abls-24.000mhz- d1x-t ilsi hc49usm-24.000000m- 2435 ael x24m000000s067 table 2.1. bill of materials for figure 2.1 em359x rev 1.0 13 3. electrical specifications 3.1. absolute maximum ratings ta b l e 3.1 lists the absolute maximu m ratings for the em359x. 3.2. recommended operating conditions ta b l e 3.2 lists the rated operating conditions of the em359x. table 3.1. absolute maximum ratings parameter test condition min max unit regulator input voltage (vdd_pads) ?0.3 +3.6 v analog, memory and core voltage (vdd_24mhz, vdd_vco, vdd_rf, vdd_if, vdd_padsa, vdd_mem, vdd_pre, vdd_synth, vdd_core) ?0.3 +2.0 v voltage on rf_p,n; rf_tx_alt_p,n ?0.3 +3.6 v rf input power ? (for max level for correct packet reception see ta b l e 3.7 ) rx signal into a loss-less balun ? +15 dbm voltage on any gpio (pa[7:0], pb[7:0], pc[7:0], pd[4:1], pe[3:0]), sw clk, nreset, vreg_out ?0.3 vdd_pads +0.3 v voltage on any gpio pin (pa4, pa5, pb5, pb6, pb7, pc1), when used as an input to the general purpose adc ?0.3 2.0 v voltage on osca, oscb, nc ?0.3 vdd_padsa +0.3 v storage temperature ?40 +140 c table 3.2. operating conditions parameter test condition min typ max unit regulator input voltage (vdd_pads) 2.1 ? 3.6 v analog and memory input voltage (vdd_24mhz, vdd_vco, vdd_rf, vdd_if, vdd_padsa, vdd_mem, vdd_pre, vdd_synth) 1.7 1.8 1.9 v core input voltage when supplied from internal regulator (vdd_core) 1.18 1.25 1.32 v operating temperature range ?40 ? +85 c em359x 14 rev 1.0 3.3. environmental characteristics ta b l e 3.3 lists the rated environmental characteristics of the em359x. 3.4. dc electrical characteristics ta b l e 3.4 lists the dc electrical characteristics of the em359x. table 3.3. environmental characteristics parameter test condition min typ max unit esd (human body model) on any pin ? ? 2 kv esd (charged device model) non-rf pins ? ? 400 v esd (charged device model) rf pins ? ? 225 v table 3.4. dc characteristics parameter test condition min typ max unit regulator input voltage (vdd_pads) 2.1 ? 3.6 v power supply range (vdd_mem) regulator output or external input 1.7 1.8 1.9 v power supply range (vdd_core) regulator output 1.18 1.25 1.32 v deep sleep current quiescent current, internal oscilla - tor disabled, 4 kb ram retained ?40 c, vdd_pads=3.6 v ? 0.9 ? ? a +25 c, vdd_pads=3.6 v ? 1.0 ? ? a +85 c, vdd_pads=3.6 v ? 2.2 ? ? a quiescent current, including ? internal rc oscillator, 4 kb ram retained ?40 c, vdd_pads=3.6 v ? 1.2 ? ? a +25 c, vdd_pads=3.6 v ? 1.25 ? ? a +85c, vdd_pads=3.6 v ? 2.5 ? ? a quiescent current, including 32.768 khz oscillator, 4 kb ram retained ?40 c, vdd_pads=3.6 v ? 1.3 ? ? a +25 c, vdd_pads=3.6 v ? 1.6 ? ? a +85 c, vdd_pads=3.6 v ? 2.9 ? ? a quiescent current, including ? internal rc oscillator and 32.768 khz oscillator, 4 kb ram retained ?40 c, vdd_pads=3.6 v ? 1.6 ? ? a +25 c, vdd_pads=3.6 v ? 1.9 ? ? a +85 c, vdd_pads=3.6 v ? 3.2 ? ? a additional quiescent current per ? 4 kb block of ram retained ?40 c, vdd_pads=3.6 v ? 0.007 ? ? a +25 c, vdd_pads=3.6 v ? 0.067 ? ? a +85 c, vdd_pads=3.6 v ? 0.76 ? ? a additional quiescent current when retained ram exceeds 32 kb ?40 c, vdd_pads=3.6 v ? 0.57 ? ? a +25 c, vdd_pads=3.6 v ? 0.67 ? ? a +85 c, vdd_pads=3.6 v ? 2.0 ? ? a simulated deep sleep (debug mode) current with no debugger activity ? 500 ? ? a em359x rev 1.0 15 reset current quiescent current, nreset asserted typ at 25 c/3.0 v max at 85 c/3.6 v ? 2 3 ma processor and peripheral currents arm ? cortex tm -m3, ram, and flash memory 25 c, 1.8 v memory and 1.25 v core arm ? cortex tm -m3 running at 12 mhz from crystal oscillator radio and all peripherals off ? 7.5 ? ma arm ? cortex tm -m3, ram, and flash memory 25 c, 1.8 v memory and 1.25 v core arm ? cortex tm -m3 running at 24 mhz from crystal oscillator radio and all peripherals off ? 8.5 ? ma arm ? cortex tm -m3, ram, and flash memory sleep current 25 c, 1.8 v memory and 1.25 v core arm ? cortex tm -m3 sleeping, cpu clock set to 12 mhz from the crystal oscillator radio and all peripherals off ? 4.0 ? ma arm ? cortex tm -m3, ram, and flash memory sleep current 25 c, 1.8 v memory and 1.25 v core arm ? cortex tm -m3 sleeping, cpu clock set to 6 mhz from the high fre - quency rc oscillator radio and all peripherals off ? 2.5 ? ma serial controller current for each controller at maximum data rate ? 0.2 ? ma general purpose timer current for each timer at maximum clock rate ? 0.25 ? ma general purpose adc current at maximum sample rate, dma enabled ? 1.1 ? ma usb active current 1 ma usb suspended mode current 1.8 v memory and 1.25 v core arm ? cortex tm -m3 sleeping, cpu clock set to 3 mhz from the high fre - quency rc oscillator. radio and all peripherals off 2.5 ma rx current radio receiver, mac, and base - band arm ? cortex tm -m3 sleeping, cpu clock set to 12 mhz ? 23.5 ? ma total rx current ( = i radio receiver, mac and baseband, cpu + iram, and flash memory ) 25 c, vdd_pads=3.0 v arm ? cortex tm -m3 running at 12 mhz ? 25.5 ? ma 25 c, vdd_pads=3.0 v arm ? cortex tm -m3 running at 24 mhz ? 27.0 ? ma table 3.4. dc characteristics (continued) parameter test condition min typ max unit em359x 16 rev 1.0 boost mode total rx current ( = i radio receiver, mac and base - band, cpu+ iram, and flash memory ) 25 c, vdd_pads=3.0 v arm ? cortex tm -m3 running at 12 mhz ? 27.5 ? ma 25 c, vdd_pads=3.0 v arm ? cortex tm -m3 running at 24 mhz ? 29.5 ? ma tx current radio transmitter, mac, and base - band 25 c and 1.8 v core; max. power out (+3 dbm typical) arm ? cortex tm -m3 sleeping, cpu clock set to 12 mhz ? 27.5 ? ma total tx current ( = i radio transmit - ter, mac and baseband, cpu + iram, and flash memory) 25 c, vdd_pads=3.0 v maximum power setting (+8 dbm); arm ? cortex tm -m3 running at 12 mhz ? 44 ? ma 25 c, vdd_pads=3.0 v +3 dbm power setting arm ? cortex tm -m3 running at 12 mhz ? 29.5 ? ma 25 c, vdd_pads=3.0 v 0 dbm power setting arm ? cortex tm -m3 running at 12 mhz ? 29 ? ma 25 c, vdd_pads=3.0 v minimum power setting arm ? cortex tm -m3 running at 12 mhz ? 24 ? ma 25 c, vdd_pads=3.0 v maximum power setting (+8 dbm) arm ? cortex tm -m3 running at 24 mhz ? 41 ? ma 25 c, vdd_pads=3.0 v +3 dbm power setting arm ? cortex tm -m3 running at 24 mhz ? 31.5 ? ma 25 c, vdd_pads=3.0 v 0 dbm power setting arm ? cortex tm -m3 running at 24 mhz ? 29 ? ma 25 c, vdd_pads=3.0 v minimum power setting arm ? cortex tm -m3 running at 24 mhz ? 23.5 ? ma table 3.4. dc characteristics (continued) parameter test condition min typ max unit em359x rev 1.0 17 figure 3.1 shows the variation of current in transmit mode (with the arm ? cortex tm -m3 running at 12 mhz). figure 3.1. transmit power consumption em359x 18 rev 1.0 figure 3.2 shows typical output power against power se tting on the silicon l abs reference design. figure 3.2. transmit output power em359x rev 1.0 19 3.5. digital i/o specifications ta b l e 3.5 lists the digital i/o specifications for the em359x . the digital i/o power (named vdd_pads) comes from three dedicated pins (pins 27, 35, and 44). the vo ltage applied to these pins sets the i/o voltage. table 3.5. digital i/o specifications parameter test condition min typ max unit voltage supply (regulator input voltage) 2.1 ? 3.6 v low schmitt switching threshold v swil schmitt input threshold going from high to low 0.42 x vdd_pads ? 0.50 x vdd_pads v high schmitt switching threshold v swih schmitt input threshold going from low to high 0.62 x vdd_pads ? 0.80 x vdd_pads v input current for logic 0 i il ? ? ?0.5 a input current for logic 1 i ih ? ? +0.5 a input pull-up resistor value r ipu 24 29 34 k ? input pull-down resistor value r ipd 24 29 34 k ? output voltage for logic 0 v ol (i ol = 4 ma for standard pads, 8 ma for high current pads) 0 ? 0.18 x vdd_pads v output voltage for logic 1 v oh (i oh = 4 ma for standard pads, 8 ma for high current pads) 0.82 x vdd_pads ? vdd_pads v output source current ? (standard current pad) i ohs ? ? 4 ma output sink current ? (standard current pad) i ols ? ? 4 ma output source current ? high current pad: pa6, pa7, pb6, pb7, pc0 i ohh ? ? 8 ma output sink current ? high current pad: pa6, pa7, pb6, pb7, pc0 i olh ? ? 8 ma total output current (for i/o pads) i oh + i ol ? ? 40 ma em359x 20 rev 1.0 ta b l e 3.6 lists the nreset pin specifications for the em35 9x. the digital i/o power (named vdd_pads) comes from three dedicated pins (pins 27, 35, and 44). the voltage applied to these pins sets the i/o voltage. 3.6. non-rf system electrical characteristics ta b l e 3.7 lists the non-rf s ystem level characteristics for the em359x. table 3.6. nreset pin specifications parameter test condition min typ max unit low schmitt switching threshold v swil schmitt input threshold going from high to low 0.42 x vdd_pads ? 0.50 x vdd_pads v high schmitt switching threshold v swih schmitt input threshold going from low to high 0.62 x vdd_pads ? 0.80 x vdd_pads v input current for logic 1 i ih ? ? +0.5 a input pull-up resistor value r ipu pull-up value while the chip is not reset 24 29 34 k ? input pull-up resistor value r ipureset pull-up value while the chip is reset 12 14.5 17 k ? table 3.7. non-rf system electrical characteristics parameter test condition min typ max unit system wake time from deep sleep from wakeup event to first arm ? cor - tex tm -m3 instruction running from 6 mhz internal rc clock includes supply ramp time and oscillator startup time ? 110 ? s shutdown time going into deep sleep from last arm ? cortex tm -m3 instruction to deep sleep mode ? 5 ? s em359x rev 1.0 21 3.7. rf electric al characteristics 3.7.1. receive ta b l e 3.8 lists the key parameters of the integrated ieee 802.15.4-2003 receiver on the em359x. receive measurements were collected with the silicon labs em359x ceramic bal un characterization module (version p1) at 2440 mhz. the typical number indicates one standa rd deviation above the mean, measured at room temperature (25 ? ? c). the min and max numbers were measured over process corners at room temperature. table 3.8. receive characteristics parameter test condition min typ max unit frequency range 2400 ? 2500 mhz sensitivity (boost mode) 1% per, 20 byte packet defined by ieee 802.15.4-2003 ? ?102 ? dbm sensitivity 1% per, 20 byte packet defined by ieee 802.15.4-2003 ? ?100 ? dbm high-side adjacent channel rejection ieee 802.15.4-2003 in terferer signal, wanted ieee 802.15 .4-2003 signal at ?82 dbm ? 35 ? db low-side adjacent channel rejection ieee 802.15.4-2003 in terferer signal, wanted ieee 802.15 .4-2003 signal at ?82 dbm ? 35 ? db 2 nd high-side adjacent channel rejec - tion ieee 802.15.4-2003 in terferer signal, wanted ieee 802.15 .4-2003 signal at ?82 dbm ? 46 ? db 2 nd low-side adjacent channel rejection ieee 802.15.4-2003 in terferer signal, wanted ieee 802.15 .4-2003 signal at ?82 dbm ? 46 ? db high-side adjacent channel rejection filtered ieee 802. 15.4-2003 inter - ferer signal, wanted ieee 802.15.4- 2003 signal at ?82 dbm ? 39 ? db low-side adjacent channel rejection filtered ieee 802. 15.4-2003 inter - ferer signal, wanted ieee 802.15.4- 2003 signal at ?82 dbm ? 47 ? db 2 nd high-side adjacent channel ? rejection filtered ieee 802. 15.4-2003 inter - ferer signal, wanted ieee 802.15.4- 2003 signal at ?82 dbm ? 49 ? db 2 nd low-side adjacent channel rejection filtered ieee 802. 15.4-2003 inter - ferer signal, wanted ieee 802.15.4- 2003 signal at ?82 dbm ? 49 ? db high-side adjacent channel rejection cw interferer signal, wanted ieee 802.15.4-2003 signal at ?82 dbm ? 44 ? db low-side adjacent channel rejection cw interferer signal, wanted ieee 802.15.4-2003 signal at ?82 dbm ? 47 ? db em359x 22 rev 1.0 2 nd high-side adjacent channel ? rejection cw interferer signal, wanted ieee 802.15.4-2003 signal at ?82 dbm ? 59 ? db 2 nd low-side adjacent channel rejection cw interferer signal, wanted ieee 802.15.4-2003 signal at ?82 dbm ? 59 ? db channel rejection fo r all other channels ieee 802.15.4-2003 in terferer signal, wanted ieee 802.15 .4-2003 signal at ?82 dbm ? 40 ? db 802.11g rejection centered at +12 mhz or ?13 mhz ieee 802.15.4-2003 in terferer signal, wanted ieee 802.15 .4-2003 signal at ?82 dbm ? 36 ? db maximum input signal level for correct operation 0 ? ? dbm co-channel rejection ieee 802.15.4-2003 in terferer signal, wanted ieee 802.15 .4-2003 signal at ?82 dbm ? ?6 ? dbc relative frequency error tolerance (50% greater than the 2x40 ppm required by ieee 802.15.4-2003) ?120 ? +120 ppm relative timing error tolerance (50% greater than the 2x40 ppm required by ieee 802.15.4-2003) ?120 ? +120 ppm linear rssi range as defined by ieee 802.15.4-2003 40 ? ? db rssi range ?90 ? ?40 dbm table 3.8. receive characteristics (continued) parameter test condition min typ max unit em359x rev 1.0 23 figure 3.3 shows the variation of receive sensitivity with temp erature for boost mode and normal mode for a typical chip. figure 3.3. receive sensitivity vs. temperature em359x 24 rev 1.0 3.7.2. transmit ta b l e 3.9 lists the key parameters of the integrated ieee 802.15.4-2003 transmitter on the em359x. transmit measurements were collect ed with the silicon labs em359x ceramic balun reference design (version a0) at 2440 mhz. the typical number indicates one standard deviation below the mean, measured at room temperature (25 ? ? c). the min and max numbers were measured over process corners at room temperature. in terms of impedance, this reference design presents a 3.9-nh inductor in parallel with a 100:50 ? balun to the rf pins. table 3.9. transmit characteristics parameter test condition min typ max unit maximum output power ? (boost mode) at highest boost mode power setting (+8) ? 8 ? dbm maximum output power at highest normal mode power setting (+3) 1 5 ? dbm minimum output power at lowest power setting ? ?55 ? dbm error vector magnitude ? (offset-evm) as defined by ieee 802.15.4-2003, which sets a 35% maximum ? 5 15 % carrier frequency error ?40 ? +40 ppm psd mask relative 3.5 mhz away ?20 ? ? db psd mask absolute 3.5 mhz away ?30 ? ? dbm em359x rev 1.0 25 figure 3.4 shows the variation of transmit power with temper ature for maximum boost mode power, and normal mode for a typical chip. figure 3.4. transmit power vs. temperature em359x 26 rev 1.0 3.7.3. synthesizer ta b l e 3.10 lists the key parameters of the in tegrated synthesizer on the em359x. table 3.10. synthesizer characteristics parameter test condition min typ max unit frequency range 2400 ? 2500 mhz frequency resolution ? 11.7 ? khz lock time from off ? ? 100 s relock time channel change or rx/tx turnaround (ieee 802.15.4-20 03 defines 192 s turnaround time) ? ? 100 s phase noise at 100 khz offset ? ?75 ? dbc/hz phase noise at 1 mhz offset ? ?100 ? dbc/hz phase noise at 4 mhz offset ? ?108 ? dbc/hz phase noise at 10 mhz offset ? ?114 ? dbc/hz em359x rev 1.0 27 4. em359x system overview figure 4.1 shows a detailed block diagram of the em359x. figure 4.1. em359x block diagram the em359x radio receiver is a low-if, super-heterodyne re ceiver. the architecture has been chosen to optimize co-existence with other devices in the 2.4 ghz band (namely wi-fi and bluetooth), and to minimize power consumption. the receiver uses differential signal paths to reduce sensitivit y to noise interference. following rf amplification, the signal is downconv erted by an image-rejecting mixer, filtered, and then digitized by an adc. the digital section of the receiver uses a coherent demo dulator to generate symbols for the hardware-based mac. the digital receiver also contains the analog radio calibra tion routines, and controls the gain within the receiver path. the radio transmitter uses an efficient architecture in which the data stream directly modulates the vco frequency. an integrated pa provides the output power. digital logi c controls tx path and output power calibration. if the em359x is to be used with an external pa, use the tx_a ctive or ntx_active signal to control the timing of the external switching logic. the integrated 4.8 ghz vco and loop f ilter minimize off-chip circuitry. only a 24 mhz crystal with its loading capacitors is required to estab lish the pll local oscillator signal. the mac interfaces the on-chip ram to the rx and tx baseband modules. the mac provides hardware-based ieee 802.15.4-2003 packet-le vel filtering. it supplies an accurate symbol time ba se that minimizes the synchronization effort of the ember software and meets the protocol timing requirements. in addition, it provides timer and synchroniz ation assistance for the ieee 802 .15.4-2003 csma-c a algorithm. the em359x integrates hardware support for a packet tr ace module, which allows robust packet-based debug. this element is a critical compone nt of ember desktop, the ember development environment, and provides advanced network debug capa bility when used with the ember debug adapter (isa3). adc rf_p,n program flash 256/512 kb data ram 32/64 kb hf ? crystal ? osc lf ? crystal ? osc general purpose adc serial wire and jtag debug internal lf rc-osc gpio multiplexor switch chip manager 1.8v ? regulator bias 2 nd level interrupt controller rf_tx_alt_p,n osca oscb pa[7:0], pb[7:0], pc[7:0], pd[4:1], pe[3:0] encryption ? acclerator if always powered domain arm ? cortex tm -m3 cpu with nvic and mpu vreg_out watchdog pa ? select lna pa pa dac mac + baseband sleep timer por nreset general ? purpose ? timers gpio registers uart/spi/ twi synth internal hf rc-osc tx_active calibration adc packet ? trace cpu debug tpiu/ itm/fpb/dwt/ etm 1.25v ? regulator vdd_core usb device swclk, ? jtck ? em359x 28 rev 1.0 the em359x integrates an arm ? cortex tm -m3 microprocessor, revision r1p1. this industry-leading core provides 32-bit performance and is very power-efficien t. it has excellent code density using the arm ? thumb-2 instruction set. the processor can be operated at 12 or 24 mhz when using the hi gh-frequency crystal oscillator, or at 6 mhz or 12 mhz when using the high-f requency internal rc oscillator. em359x parts have either 256 or 512 kb of flash memory and either 32 or 64 kb of ram on-chip, and the arm configurable memory protection unit (mpu). the em359x implements both the arm serial wire and jt ag debug interfaces. these interfaces provide real time, non-intrusive prog ramming and debugging capabilitie s. serial wire and jtag pr ovide the same functionality, but are mutually exclusive. the serial wi re interface uses two pins; the jtag interface uses five. serial wire is preferred, since it uses fewer pins. the em359x contains the arm ? embedded trace macrocell (etm) to provide advanced real time software debugging features for complex systems. the em359x contains 32 gpio pins shared with other perip heral or alternate functions. because of flexible routing within the em359x, external devices can use the alternate fu nctions on a variety of different gpios. the integrated serial controllers sc1 and sc3 can be configured for spi ( master or slave), twi (master-only), or uart operation, and the serial controllers sc2 and sc4 can be configured for spi (master or slave) or twi (master-only) operation. the em359x has an optional integrated usb 2.0-compliant, full-speed (12 mbps) device peripheral, with an on- chip transceiver. it is available on gpio pins. the em359x has a general purpose adc which can sample an alog signals from six gpio pins in single-ended or differential modes. it can also sample the 1.8 v regu lated supply vdd_padsa, the voltage reference vref, and gnd. the adc has one voltage range: 0 v to 1.2 v (normal). the adc has a dma mode to capture samples and automatically transfer them into ram. the integrated volt age reference for the adc, vref, can be made available to external circuitry. an external voltage reference can also be driven into the adc. the regulator input voltage, vdd_pads, cannot be measured using the general pu rpose adc, but it can be measured through ember software. the em359x contains four os cillators: a high-frequency 24 mhz external crystal osc illator, a high-frequency 12 mhz internal rc oscillator, an optional low-frequency 32.768 khz external crystal oscilla tor, and a low-frequency 10 khz internal rc oscillator. the em359x has an ultra low power, deep sleep state with a choice of clocking modes. the sleep timer can be clocked with either the external 32.768 khz crystal oscillator or with a 1 khz clock derived from t he internal 10 khz rc oscillator. alternatively, all clocks can be disabled fo r the lowest power mode. in the lowest power mode, only external events on gpio pins will wake up the chip. the em359x has a fa st startup time (typically 110 s) from deep sleep to the execution of the first arm ? cortex tm -m3 instruction. the em359x contains three power domains. the always-on hi gh voltage supply powers the gpio pads and critical chip functions. regulated low voltage supplies power the rest of the chip. the low voltage supplies are disabled during deep sleep to reduce power consumption. integrated voltage regulators generate regulated 1.25 v and 1.8 v voltages from an unregulated supply voltage. the 1.8 v regulator output is decoupled and routed externally to supply analog blocks, ram, and flash memories. the 1.25 v regulator output is decoupl ed externally and supplies the core logic. the following sections summarize features of the em359x that are addressed in more detail in the ember em359x reference manual . 4.1. microprocessor and memory refer to chapter 2 in the ember em359x reference manual for more information. 4.1.1. arm ? cortex?-m3 microprocessor the em359x integrates the arm ? cortex tm -m3 microprocessor, revision r1p1, developed by arm ltd., making the em359x a true system-on-chip solution. the arm ? cortex tm -m3 is an advanced 32-bit modified harvard architecture processor that has separate internal program and data bu ses, but presents a unified program and data address space to software. em359x rev 1.0 29 4.1.2. embedded memory embedded memory consists of flash memory and ram. the em359x provides a total of either 256 or 512 kb of flash memory (256 kb for EM3591/2 and 512 kb for em3595/6/7/8). the flash memory is provided in three separate blocks: ?? main flash block (mfb) ?? fixed information block (fib) ?? customer information block (cib) the em359x has either 32 or 64 kb of static ram on -chip (32 kb for EM3591/2/5/6 and 64 kb for em3597/8). although the arm ? cortex tm -m3 allows bit band accesses to this address region, the standard mpu configuration does not permit use of the bit-band feature. the ram is physically conn ected to the ahb system bus and is therefore accessible to both the arm ? cortex tm -m3 microprocessor and the debugger. the radio (802.15.4-2003 mac), general purpose adc, usb device controller, and the four serial controllers are equipped with dma controllers, which allow them to transfer data into and out of ram autonomously. 4.2. interrupt system the em359x?s interrupt system is composed of two parts: a standard arm ? cortex tm -m3 nested vectored interrupt controller (nvic) that provides top-level interr upts, and a proprietary event manager (em) that provides second-level interrupts. the nvic and em provide a simple hierarchy. all second-level interrupts from the em feed into top-level interrupts in the nvic. this two-level hierarchy allows fo r both fine granular control of interrupt sources and coarse granular control over entire peripherals, while allowing peripherals to have their own interrupt vector. refer to chapter 3 in the ember em359x reference manual for more information. 4.2.1. nested vectored interrupt controller (nvic) the arm ? cortex tm -m3 nested vectored interrupt co ntroller (nvic) facilitates low- latency exceptio n and interrupt handling. the nvic and the processor core interface ar e closely coupled, which enables low-latency interrupt processing and efficient processing of late-arriving interrupts. the nvic maintains knowledge of the stacked (nested) interrupts to enable tail-chaining of interrupts. the nvic also contains a software-configurable interrupt prioritization mechanism. 4.2.2. event manager the proprietary event manager provides second-level in terrupts. the event manager takes a large variety of hardware interrupt sources from the peripherals and merges them into a smaller group of interrupts in the nvic. effectively, all second-level interrupts from a peripheral are ?or?d? together into a single interrupt in the nvic. in addition, the event manager provides missed indicators fo r the top-level peripheral interrupts with the register int_miss. 4.2.3. memory protection unit the em359x includes the arm ? cortex tm -m3 memory protection unit, or mpu. the mpu controls access rights and characteristics of up to eight address regions, each of which may be divided into eight equal sub-regions. refer to the arm ? cortex tm -m3 technical reference manual (ddi 0337a) for a detailed description of the mpu. 4.3. radio module the radio module consists of an analog front end and digital baseband. refer to chapter 4 in the ember em359x reference manual for more information. 4.3.1. receive (rx) path the em359x rx path uses a low-if, super-heterodyne re ceiver that rejects the image frequency using complex mixing and polyphase filtering. the filt ering within the rx path improves the em359x?s co-existence with other 2.4 ghz transceivers such as zigbee/ 802.15.4-2003, ieee 802 .11-2007, and bluetooth radios. the digital baseband also provides gain control of the rx path, both to enable the reception of small and large wanted signals and to tolerate large interferers. em359x 30 rev 1.0 4.3.2. transmit (tx) path the em359x tx path produces an o-qpsk-modulated signa l using the analog front end and digital baseband. the area- and power-efficient tx architecture uses a two-point modulation scheme to modulate the rf signal generated by the synthesizer. the modulated rf signal is fed to the integrated pa and then out of the em359x. 4.3.3. integrated mac module the em359x integrates most of the ieee 802.15.4-200 3 mac requirements in hardwa re. this allows the arm ? cortex tm -m3 cpu to provide greater bandwidth to application and network operations. in addition, the hardware acts as a first-line filter for unwanted packets. the em359x mac uses a dma interface to ram to further reduce the overall arm ? cortex tm -m3 cpu interaction when transmitting or receiving packets. the primary features of the mac are: ?? crc generation, append ing, and checking ?? hardware timers and interrupts to achieve the mac symbol timing ?? automatic preamble and sfd pre-pending on tx packets ?? address recognition and packet filtering on rx packets ?? automatic acknowledgement transmission ?? automatic transmission of packets from memory ?? automatic transmission after backoff time if channel is clear (cca) ?? automatic acknowledgement checking ?? time stamping received and transmitted messages ?? attaching packet information to received packets (lqi, rssi, gain, time stamp, and packet status) ?? eee 802.15.4-2003 timi ng and slotted/unslotted timing 4.3.4. packet trace interface (pti) the em359x integrates a true phy-level pti with the mac, allowing complete, non-intrusive capture of all packets to and from the em359x with ember development tools. 4.3.5. random number generator thermal noise in the analog circuitry is digitized to provide entropy for a true random number generator (trng). ember software uses the trng to seed a pseudo ran dom number generator (prng). the trng is also used directly for cryptographic key generation. 4.4. system modules system modules encompass power domains, resets, clo cks, system timers, power management, and encryption. refer to chapter 5 in the ember em359x reference manual for more information. 4.4.1. power domains the em359x contains three power domains: ?? an ?always-on domain? containing all logic and analog cells required to manage the em359x?s power modes, including the gpio controller and sl eep timer. this domain must remain powered. ?? a ?core domain? containing the cpu, nested vector ed interrupt controller (nvic), and peripherals. to save power, this domain can be powered down usin g a mode called deep sleep. in the em359x the core domain also includes the ram, which by default is pow ered down in deep sleep. an additional feature of the ram is that blocks of ram cells can optionally be retained in deep sleep. this is configured using a register, which must be written before entering deep sleep. ?? a ?flash domain? containing the flash memory. this domain is managed by the power management controller. during deep sleep the flash portion is completely powered down. the preferred and recommended power configuration is to use the internal regulated power supplies to provide power to the core and memory domains. optionally, the on-chip regulators may be left unused, and the core and memory domains may instead be powered from external supplies. refer to chapter 6 in the ember em359x reference manual for more information. em359x rev 1.0 31 4.4.2. resets the em359x resets are generated from a number of sources. each of these reset sources feeds into central reset detection logic that causes various parts of the system to be reset depending on the state of the system and the nature of the reset event. reset sources include: ?? power-on-resets (por hv and por lv) ?? nreset pin ?? watchdog reset ?? software reset ?? option byte error ?? debug reset ?? jrst ?? deep sleep reset the em359x records the last reset cond ition that generated a restart to the system. the reset generation module responds to reset sources and genera tes reset signals, which vary base d on the reset source and cause. 4.4.3. clocks the em359x integrates four oscillators: ?? 12 mhz rc oscillator: used as the default system clock source when po wer is applied to the core domain. ?? 24 mhz crystal oscillator: requires an external 24 mhz crystal. used as the system clock source when all peripherals, including the radio periphe ral, require the most accurate clock. ?? 10 khz rc oscillator: provided as an inter nal timing reference ?? 32.768 khz crystal oscillator: provided as an optional timing reference for on-chip timers. 4.4.4. system timers the em359x contains three system timers: ?? watchdog timer: can be enabled to provide protection against software crashes and arm ? cortex tm -m3 cpu lockup. ?? sleep timer: 32-bit timer dedicated to system timi ng and waking from sleep at specific times. ?? event timer: an arm ? standard system timer in the nvic. 4.4.5. power management the em359x?s power management system is designed to achieve the lowest deep sleep current consumption possible while still providing flexible wakeup sources, timer activity, an d debugger operation. the em359x has four main sleep modes: ?? idle sleep: puts the cpu into an idle state where execution is suspended until any interrupt occurs. all power domains remain fully powered and nothing is reset. ?? deep sleep 1: the primary deep sleep state. in this state, the core power domain is fully powered down and the sleep timer is active. ?? deep sleep 2: the same as deep sl eep 1 except that the sleep timer is inactive to save power. in this mode the sleep timer cannot wake up the em359x. ?? deep sleep 0 (also known as emulated deep sleep) : the chip emulates a true deep sleep without powering down the core domain. instead, the core domain remains powered and all peripherals except the system debug components (itm, dwt, fpb, nvic) are held in reset. the purpose of this sleep state is to allow em359x software to perform a deep sleep cycle while maintaining debug configuration such as breakpoints. the deep sleep modes consume less than 2 a power. when in deep sleep the em359x can be returned to the running state in a number of ways. the wake sources are split depending on deep sleep 1 or deep sleep 2. the ram can optionally be configured to select banks of locations to be non-volatile. in deep sleep those banks selected are powered by a low leakage internal regulato r that remains on during deep sleep, powered from the always-on supply. em359x 32 rev 1.0 4.5. integrated voltage regulator the em359x integrates two low dropout regulators to pr ovide 1.8 v and 1.25 v power supplies. the 1v8 regulator supplies the analog and memories, and the 1v25 regulator supplies the digital core. in deep sleep the voltage regulators are disabled. an external 1.8 v regulator ma y replace both internal regulators. the always-on domain needs to be minimally powered at 2.1 v, and can not be powered from the external 1.8 v regulator. refer to chapter 6 in the ember em359x reference manual for more information. 4.6. peripherals 4.6.1. gpio the em359x has 32 multi-purpose gpio pins , which may be individually configured as: ?? general purpose output ?? general purpose open-drain output ?? alternate output controlled by a peripheral device ?? alternate open-drain output controlled by a peripheral device ?? analog ?? general purpose input ?? general purpose input with pull-up or pull-down resistor the 32 gpio pins are grouped into five ports. each pin has a 4-bit configuration value in its gpio_pxcfgh/l register. if a gpio has two peripherals that can be the sour ce of alternate output mode data, then other registers in addition to gpio_pxcfgh/l determine which periph eral controls the output. for some gpios the gpio_pxcfgh/l configuration will be overridden. these functi ons are forced when the em359x is reset and remain forced until software or an external debugger overrides the forced functions. refer to chapter 7 in the ember em359x reference manual for more information. 4.6.2. serial controllers the em359x has four serial controllers , sc1, sc2, sc3, and sc4, which provide several options for full-duplex synchronous and asynchronous serial communications. ?? spi (serial peripheral interface), master or slave ?? twi (two wire serial interface), master only ?? uart (universal asynchronous receiver/transmitter), sc1 and sc3 only ?? receive and transmit fifos and dma channels, spi and uart modes the sc1, sc2, sc3, and sc4 spi controllers include an spi master controller with the following features: ?? full duplex operation ?? programmable clock frequency (12 mhz max.) ?? programmable clock polarity and phase ?? selectable data shift direction (either lsb or msb first) ?? receive and transmit fifos ?? receive and transmit dma channels the sc1, sc2, sc3, and sc4 spi controllers incl ude a spi slave controller with these features: ?? full duplex operation ?? up to 5 mbps data transfer rate ?? programmable clock polarity and clock phase ?? selectable data shift direction (either lsb or msb first) ?? slave select input sc1, sc2, sc3, and sc4 include a two wire serial interf ace (twi) master controller wi th the following features: ?? uses only two bidirectional gpio pins ?? programmable clock frequency (up to 400 khz) ?? supports both 7-bit and 10-bit addressing em359x rev 1.0 33 ?? compatible with philips? i2c-bus sl ave devices the sc1 and sc3 uart supports the following features: ?? flexible baud rate clock (300 bps to 921.6 kbps) ?? data bits (7 or 8) ?? parity bits (none, odd, or even) ?? stop bits (1 or 2) ?? false start bit and noise filtering ?? receive and transmit fifos ?? optional rts/cts flow control ?? receive and transmit dma channels receive and transmit fifos allow faster data speeds usi ng byte-at-a-time interrupts. for the highest spi and uart speeds, dedicated receive and transmit dma channe ls reduce cpu loading and extend the allowable time to service a serial controller interrupt. refer to chapter 8 in the ember em359x reference manual for more information. 4.6.3. usb it supports up to six endpoints (in addition to the control en dpoint 0). there are five endpoints that can be used as either interrupt or bulk and one isochronous endpoint. the usb peripheral is interfaced to the cpu through mem ory mapped registers for control, and dma for data. the usb device generates its own 48 mhz internal clock from the main 24 mhz crystal clock. the em359x, where applicable, fully supports usb susp end and resume modes, and meets the usb specification suspend current of <2.5ma. it achieves this by switching th e chip to run from a divided down version of the system clock. refer to chapter 9 in the ember em359x reference manual for more information. 4.6.4. general purpose timers each of the em359x?s two general-purpose timers co nsists of a 16-bit auto-reload counter driven by a programmable prescaler. they may be used for a variety of purposes, including meas uring the pulse lengths of input signals (input capture) or generating output waveforms (output compare and pwm). pulse lengths and waveform periods can be modulated fr om a few microseconds to several m illiseconds using the timer prescaler. the timers are completely independent, and do not shar e any resources. they can be synchronized together. the two general-purpose timers, tim1 a nd tim2, have the following features: ?? 16-bit up, down, or up/down auto-reload counter. ?? programmable prescaler to divide the counter clock by any power of two from 1 through 32768. ?? 4 independent channels for: ?? input capture ?? output compare ?? pwm generation (edge- and center-aligned mode) ?? one-pulse mode output ?? synchronization circuit to contro l the timer with external signals and to interconnect the timers. ?? flexible clock source selection: ?? peripheral clock (pclk at 6 or 12 mhz) ?? 32.768 khz external clock (if available) ?? 1 khz clock ?? gpio input ?? interrupt generation on the following events: ?? update: counter overflow/underflow , counter initialization (software or internal/external trigger) ?? trigger event (counter start, stop, initializa tion or count by internal/external trigger) ?? input capture ?? output compare em359x 34 rev 1.0 ?? supports incremental (quadrature) encoders and hall sensors for positioning applications. ?? trigger input for external clock or cycle-by-cycle current management. refer to chap ter 10 in the ember em359x reference manual for more information. 4.6.5. analog-to-digital converter (adc) the em359x adc is a first-order sigma-del ta converter with the following features: ?? resolution of up to 14 bits ?? sample times as fast as 5.33 s (188 khz) ?? differential and single-ended conversions from six external and four internal sources ?? one voltage range (differe ntial): -vref to +vref ?? choice of internal or external vref ?? internal vref may be output to pb0 or external vref may be derived from pb0 ?? digital offset and gain correction ?? dedicated dma channel with one-shot and continuous operating modes refer to chapte r 11 in the ember em359x reference manua l for more information. 4.7. debugging the em359x utilizes standard se rial wire and jtag interf aces for powe rful software debuggi ng and pr ogramming of the arm ? cortex tm -m3 core. the em359x integrates the standard arm ? system debug components: flash patch and breakpoint (fpb), data watchpoint and trac e (dwt), and instrumentatio n trace macrocell (itm) as well as the advanced embedded trace macrocell (etm). 4.7.1. trace port interface unit (tpiu) the em359x integrates the standard arm? trace port inte rface unit (tpiu). the tpiu receives a data stream from the on-chip trace data generated by the standard arm ? instrument trace macrocell (itm) and arm? embedded trace macrocell (etm), buffers the data in a fifo for the itm and fifo for the etm, formats the data, and serializes the data to be sent off chip through alternate functions of the gpio. refer to chap ter 12 in the ember em359x reference manual for more information. 4.7.2. instrumentation trace macrocell (itm) the em359x integrates the standard arm ? instrumentation trace macrocell (itm). the itm is an application- driven trace source that su pports printf style debugging to trace soft ware events and emits diagnostic system information from the arm ? data watchpoint and trace (dwt). software using the itm generates software instrumentation trace (swit). in addition, the itm provides coarse-grained timestamp functionality. refer to chap ter 13 in the ember em359x reference manual for more information. 4.7.3. embedded trace macrocell (etm) the em359x integrates the standard arm ? embedded trace macrocell (etm) version 3.4. the etm is a powerful debug component that enables reconstruction of program execution. it is designed as a high-speed, low-power debug tool that only supp orts instruction trace. refer to chap ter 14 in the ember em359x reference manual for more information. 4.7.4. data watchpoint and trace (dwt) the em359x integrates the standard arm? data watc hpoint and trace (dwt). the dwt provides hardware support for profiling and debugging functionalit y. the dwt offers the following features: ?? pc sampling ?? comparators to support: ?? watchpoints ? enters debug state ?? data tracing ?? cycle count matched pc sampling ?? exception trace support ?? instruction cycle count calculation support refer to chap ter 15 in the ember em359x reference manual for more information. em359x rev 1.0 35 4.7.5. flash patch and breakpoint (fpb) the em359x integrates the standard arm ? flash patch and breakpoint (fpb). the fpb implements hardware breakpoints. the fpb also provides support for remapping of specific instruction or literal locations from flash memory to an address in ram memory. the fpb contains: ?? two literal comparators for matching against liter al loads from flash space, and remapping to a corresponding ram space. ?? six instruction compar ators for matching against instruction fetches from flash space, and remapping to a corresponding ram space. alternatively, the comparators can be individually configured to return a breakpoint instructio n to the processor core on a match, impl ementing hardware br eakpoint capability. refer to chap ter 16 in the ember em359x reference manual for more information. 4.7.6. serial wire and jtag (swj) interface the em359x includes a standard serial wire and jtag (swj) interface. the swj is the primary debug and programming interface of the em359x. the swj gives debu g tools access to the internal buses of the em359x, and allows for non-intrusive memory and register access as well as cpu halt-step style debugging. therefore, any design implementing the em359x should make the swj signals readily available. serial wire is an arm ? standard, bi-directional, two-wire protocol designed to replace jtag, and provides all the normal jtag debug and test functionality. jtag is a standard five-wire protocol providing debug and test functionality. in addition, the two serial wire signals (swdio and swclk) are overlaid on two of the jtag signals (jtms and jtck). this keeps the design compact and allows debug tools to switch between serial wire and jtag as needed, without changing pin connections. while serial wire and jtag offer the same debug and test functionality, silicon labs recommends serial wire. serial wire uses only two pins instead of five, and of fers a simple communication protocol, high performance data rates, low power, built-in error detection, and protection from glitches. the swj pins are forced functions, and their correspondi ng gpio_pxcfgh/l configurations are overridden when the em359x resets. refer to chap ter 17 in the ember em359x reference manual for more information. em359x 36 rev 1.0 5. ordering information use the following part number to order the em359x: to order parts, contact silicon labs at 1+(877) 444-3032, or find a sale s office or distributor on our website, www.silabs.com . orderable part number package materials / quantity flash (kb) ram (kb) usb EM3591-rtr tape & reel, contains 2000 units/reel 256 32 no em3592-rtr tape & reel, contains 2000 units/reel 256 32 yes em3595-rtr tape & reel, contains 2000 units/reel 512 32 no em3596-rtr tape & reel, contains 2000 units/reel 512 32 yes em3597-rtr tape & reel, contains 2000 units/reel 512 64 no em3598-rtr tape & reel, contains 2000 units/reel 512 64 yes em359x rev 1.0 37 6. pin assignments figure 6.1. em359x pin definitions refer to chapter 7, gpio, in the ember em359x reference manual for details about selecting gpio pin functions. vdd_24mhz 2 vdd_vco 3 rf_p 4 rf_n 5 vdd_rf 6 rf_tx_alt_p 7 rf_tx_alt_n 8 vdd_if 9 osca 1 nc 10 pc5, tx_active 12 nreset 13 vdd_padsa 11 pc6, osc32b, ntx_active 14 pc7, osc32a, osc32_ext 15 vreg_out vdd_pads vdd_core pa7, tim1c4, reg_en pd1, sc3miso, sc3mosi, sc3sda, sc3txd pd2, sc3miso, sc3mosi, sc3scl, sc3rxd pd3, sc3ncts, sc3sclk pb3, tim2c3, sc1ncts, sc1sclk pb4, tim2c4, sc1nrts, sc1nssel pa0, usbdm, tim2c1, sc2mosi pa1, usbdp, tim2c3, sc2sda, sc2miso vdd_pads oscb vdd_synth vdd_pre vdd_core pb5, adc0, tim2clk, tim1msk pb6, adc1, irqb, tim1c1 pe3, sc4nssel pe2, sc4scl, sc4sclk pb7, adc2, irqc, tim1c2 pc0, jrst, irqd, tracedata1 vdd_mem pc1, adc3, tracedata3 vdd_pads pb0, vref, irq , tracedata2, tim1clk, tim2msk 16 17 18 19 20 21 22 23 24 25 26 27 43 pc4, jtms, swdio pc3, jtdi, traceclk pc2, jtdo, swo, tracedata0 swclk, jtck pb2, sc1miso, sc1mosi, sc1scl, sc1rxd, tim2c2 pb1, sc1miso, sc1mosi, sc1sda, sc1txd, tim2c1 pa6, tim1c3 vdd_pads pe1, sc4sda, sc4miso pe0, sc4mosi pd4, sc3nrts, sc3nssel pa5, adc5, pti_data, nbootmode, tracedata3 pa4, adc4, pti_en, tracedata2 pa3, sc2nssel, tim2c ? 29 30 31 32 33 34 35 36 37 38 39 40 41 42 44 45 46 47 48 49 50 51 52 53 54 55 56 pa2, tim2c4, sc2scl, sc2sclk 28 em359x 38 rev 1.0 table 6.1. em359x pin descriptions pin # signal direction description 1 osca i/o 24 mhz crystal oscillator or external clock input. (an external clock input should only be used for test and debug purposes. if used in this manner, the external clock input should be a 1.8 v, 50% duty cycle, square wave.) 2 vdd_24mhz power 1.8 v high-frequency oscillator supply 3 vdd_vco power 1.8 v vco supply 4 rf_p i/o differential (with rf_n) receiv er input/transmitter output 5 rf_n i/o differential (with rf_p) receiver input/transmitter output 6 vdd_rf power 1.8 v rf supply (lna and pa) 7 rf_tx_alt_p o differential (with rf_tx_alt_n) transmitter output (optional) 8 rf_tx_alt_n o differential (with rf_tx_alt_p) transmitter output (optional) 9 vdd_if power 1.8 v if supply (mixers and filters) 10 nc do not connect 11 vdd_padsa power analog pad supply (1.8 v) 12 pc5 i/o digital i/o tx_active o logic-level control for external rx/tx switch. the em359x baseband con - trols tx_active and drives it high (vdd_pads) when in tx mode. select alternate output func tion with gpio_pccfgh[7:4] 13 nreset i active low chip rese t (internal pull-up) 14 pc6 i/o digital i/o osc32b i/o 32.768 khz crystal oscillator select analog function with gpio_pccfgh[11:8] ntx_active o inverted tx_active signal (see pc5) select alternate output func tion with gpio_pccfgh[11:8] 15 pc7 i/o digital i/o osc32a i/o 32.768 khz crystal oscillator select analog function with gpio_pccfgh[15:12] osc32_ext i digital 32.768 khz clock input source 16 vreg_out power regulator output (1.8 v while awake, 0 v during deep sleep) 17 vdd_pads power pads supply (2.1?3.6 v) note: 1. irqc and irqd external interrupts can be mapped to any digital i/o pin using the gpio_irqcsel and gpio_irqdsel registers. em359x rev 1.0 39 18 vdd_core power 1.25 v digital core supply decoupling 19 pa7 i/o high current digital i/o disable reg_en with gpio_dbgcfg[4] tim1c4 o timer 1 channel 4 output enable timer output with tim1_ccer select alternate output func tion with gpio_pacfgh[15:12] disable reg_en with gpio_dbgcfg[4] tim1c4 i timer 1 channel 4 input cannot be remapped reg_en o external regulator open drain output enabled after reset 20 pd1 i/o digital i/o sc3miso o spi slave data out of serial controller 3 select spi with sc3_mode select slave with sc3_spicfg select alternate output func tion with gpio_pdcfgl[7:4] sc3mosi o spi master data out of serial controller 3 select spi with sc3_mode select master with sc3_spicfg select alternate output func tion with gpio_pdcfgl[7:4] sc3sda i/o twi data of serial controller 3 select twi with sc3_mode select alternate open-drain output function with gpio_pdcfgl[7:4] sc3txd o uart transmit data of serial controller 3 select uart with sc3_mode select alternate output func tion with gpio_pdcfgl[7:4] table 6.1. em359x pin descriptions (continued) pin # signal direction description note: 1. irqc and irqd external interrupts can be mapped to any digital i/o pin using the gpio_irqcsel and gpio_irqdsel registers. em359x 40 rev 1.0 21 pd2 i/o digital i/o sc3miso i spi master data in of serial controller 3 select spi with sc3_mode select master with sc3_spicfg sc3mosi i spi slave data in of serial controller 3 select spi with sc3_mode select slave with sc3_spicfg sc3scl i/o twi clock of serial controller 3 select twi with sc3_mode select alternate open-drain output function with gpio_pdcfgl[11:8] sc3rxd i uart receive data of serial controller 3 select uart with sc3_mode 22 pd3 i/o digital i/o sc3ncts i uart cts handshake of serial controller 3 enable with sc3_uartcfg[5] select uart with sc3_mode sc3sclk o spi master clock of serial controller 3 enable master wi th sc3_spicfg[4] select spi with sc3_mode select alternate output func tion with gpio_pdcfgl[15:12] sc3sclk i spi slave clock of serial controller 3 enable slave with sc3_spicfg[4] select spi with sc3_mode table 6.1. em359x pin descriptions (continued) pin # signal direction description note: 1. irqc and irqd external interrupts can be mapped to any digital i/o pin using the gpio_irqcsel and gpio_irqdsel registers. em359x rev 1.0 41 23 pb3 i/o digital i/o tim2c3 (see also pin 26) o timer 2 channel 3 output enable remap with tim2_or[6] enable timer output in tim2_ccer select alternate output func tion with gpio_pbcfgl[15:12] tim2c3 (see also pin 26) i timer 2 channel 3 input enable remap with tim2_or[6] sc1ncts i uart cts handshake of serial controller 1 enable with sc1_uartcfg[5] select uart with sc1_mode sc1sclk o spi master clock of serial controller 1 either disable timer output in tim2_ccer, ? or disable remap with tim2_or[6] enable master wi th sc1_spicfg[4] select spi with sc1_mode select alternate output func tion with gpio_pbcfgl[15:12] sc1sclk i spi slave clock of serial controller 1 enable slave with sc1_spicfg[4] select spi with sc1_mode 24 pb4 i/o digital i/o tim2c4 (see also pin 28) o timer 2 channel 4 output enable remap with tim2_or[7] enable timer output in tim2_ccer select alternate output func tion with gpio_pbcfgh[3:0] tim2c4 (see also pin 28) i timer 2 channel 4 input enable remap with tim2_or[7] sc1nrts o uart rts handshake of serial controller 1 either disable timer output in tim2_ccer, ? or disable remap with tim2_or[7] enable with sc1_uartcfg[5] select uart with sc1_mode select alternate output func tion with gpio_pbcfgh[3:0] sc1nssel i spi slave select of serial controller 1 enable slave with sc1_spicfg[4] select spi with sc1_mode table 6.1. em359x pin descriptions (continued) pin # signal direction description note: 1. irqc and irqd external interrupts can be mapped to any digital i/o pin using the gpio_irqcsel and gpio_irqdsel registers. em359x 42 rev 1.0 25 pa0 i/o digital i/o usbdm (where applicable) i/o usb d- signal select analog function with gpio_pacfgl[3:0] tim2c1 (see also pin 35) o timer 2 channel 1 output disable remap with tim2_or[4] enable timer output in tim2_ccer select alternate output function with gpio_pacfgl[3:0] tim2c1 (see also pin 35) i timer 2 channel 1 input disable remap with tim2_or[4] sc2mosi o spi master data out of serial controller 2 either disable timer output in tim2_ccer, ? or enable remap with tim2_or[4] enable master wi th sc2_spicfg[4] select spi with sc2_mode select alternate output function with gpio_pacfgl[3:0] sc2mosi i spi slave data in of serial controller 2 enable slave with sc2_spicfg[4] select spi with sc2_mode table 6.1. em359x pin descriptions (continued) pin # signal direction description note: 1. irqc and irqd external interrupts can be mapped to any digital i/o pin using the gpio_irqcsel and gpio_irqdsel registers. em359x rev 1.0 43 26 pa1 i/o digital i/o usbdp (where applicable) i/o usb d+ signal select analog function with gpio_pacfgl[7:4] tim2c3 (see also pin 23) o timer 2 channel 3 output disable remap with tim2_or[6] enable timer output in tim2_ccer select alternate output function with gpio_pacfgl[7:4] tim2c3 (see also pin 23) i timer 2 channel 3 input disable remap with tim2_or[6] sc2sda i/o twi data of serial controller 2 either disable timer output in tim2_ccer, ? or enable remap with tim2_or[6] select twi with sc2_mode select alternate open-drain output function with gpio_pacfgl[7:4] sc2miso o spi slave data out of serial controller 2 either disable timer output in tim2_ccer, ? or enable remap with tim2_or[6] enable slave with sc2_spicfg[4] select spi with sc2_mode select alternate output function with gpio_pacfgl[7:4] sc2miso i spi master data in of serial controller 2 enable slave with sc2_spicfg[4] select spi with sc2_mode 27 vdd_pads power pads supply (2.1?3.6 v) table 6.1. em359x pin descriptions (continued) pin # signal direction description note: 1. irqc and irqd external interrupts can be mapped to any digital i/o pin using the gpio_irqcsel and gpio_irqdsel registers. em359x 44 rev 1.0 28 pa2 i/o digital i/o tim2c4 (see also pin 24) o timer 2 channel 4 output disable remap with tim2_or[7] enable timer output in tim2_ccer select alternate output func tion with gpio_pacfgl[11:8] tim2c4 (see also pin 24) i timer 2 channel 4 input disable remap with tim2_or[7] sc2scl i/o twi clock of serial controller 2 either disable timer output in tim2_ccer, ? or enable remap with tim2_or[7] select twi with sc2_mode select alternate open-drain output function with gpio_pacfgl[11:8] sc2sclk o spi master clock of serial controller 2 either disable timer output in tim2_ccer, ? or enable remap with tim2_or[7] enable master wi th sc2_spicfg[4] select spi with sc2_mode select alternate output func tion with gpio_pacfgl[11:8] sc2sclk i spi slave clock of serial controller 2 enable slave with sc2_spicfg[4] select spi with sc2_mode 29 pa3 i/o digital i/o sc2nssel i spi slave select of serial controller 2 enable slave with sc2_spicfg[4] select spi with sc2_mode tim2c2 (see also pin 38) o timer 2 channel 2 output disable remap with tim2_or[5] enable timer output in tim2_ccer select alternate output func tion with gpio_pacfgl[15:12] tim2c2 (see also pin 38) i timer 2 channel 2 input disable remap with tim2_or[5] table 6.1. em359x pin descriptions (continued) pin # signal direction description note: 1. irqc and irqd external interrupts can be mapped to any digital i/o pin using the gpio_irqcsel and gpio_irqdsel registers. em359x rev 1.0 45 30 pa4 i/o digital i/o adc4 analog adc input 4 select analog function with gpio_pacfgh[3:0] pti_en o frame signal of packet trace interface (pti) disable trace interface in arm core enable pti in ember software select alternate output func tion with gpio_pacfgh[3:0] tracedata2 (see also pin 43) o synchronous cpu trace data bit 2 select 4-wire synchronous trace interface in arm core enable trace interface in arm core select alternate output func tion with gpio_pacfgh[3:0] 31 pa5 i/o digital i/o adc5 analog adc input 5 select analog function with gpio_pacfgh[7:4] pti_data o data signal of packet trace interface (pti) disable trace interface in arm core enable pti in ember software select alternate output func tion with gpio_pacfgh[7:4] nbootmode i activate fib monitor instead of main program or bootloader when coming out of reset. signal is active during and immediate ly after a reset on nreset. refer to section 7.5, boot configuration, in chapter 7, gpio, of the ember em359x reference manual for details. tracedata3 (see also pin 44) o synchronous cpu trace data bit 3 select 4-wire synchronous trace interface in arm core enable trace interface in arm core select alternate output func tion with gpio_pacfgh[7:4] 32 pd4 i/o digital i/o sc3nrts o uart rts handshake of serial controller 3 enable with sc3_uartcfg[5] select uart with sc3_mode select alternate output func tion with gpio_pdcfgh[3:0] sc3nssel i spi slave select of serial controller 3 enable slave with sc3_spicfg[4] select spi with sc3_mode table 6.1. em359x pin descriptions (continued) pin # signal direction description note: 1. irqc and irqd external interrupts can be mapped to any digital i/o pin using the gpio_irqcsel and gpio_irqdsel registers. em359x 46 rev 1.0 33 pe0 i/o digital i/o sc4mosi o spi master data out of serial controller 4 enable master wi th sc4_spicfg[4] select spi with sc4_mode select alternate output func tion with gpio_pecfgl[3:0] sc4mosi i spi slave data in of serial controller 4 enable slave with sc4_spicfg[4] select spi with sc4_mode 34 pe1 i/o digital i/o sc4sda i/o twi data of serial controller 4 select twi with sc4_mode select alternate open-drain output function with gpio_pecfgl[7:4] sc4miso o spi slave data out of serial controller 4 enable slave with sc4_spicfg[4] select spi with sc4_mode select alternate output func tion with gpio_pecfgl[7:4] sc4miso i spi master data in of serial controller 4 enable slave with sc4_spicfg[4] select spi with sc4_mode 35 vdd_pads power pads supply (2.1?3.6 v) 36 pa6 i/o high cur - rent digital i/o tim1c3 o timer 1 channel 3 output enable timer output in tim1_ccer select alternate output func tion with gpio_pacfgh[11:8] tim1c3 i timer 1 channel 3 input cannot be remapped table 6.1. em359x pin descriptions (continued) pin # signal direction description note: 1. irqc and irqd external interrupts can be mapped to any digital i/o pin using the gpio_irqcsel and gpio_irqdsel registers. em359x rev 1.0 47 37 pb1 i/o digital i/o sc1miso o spi slave data out of serial controller 1 either disable timer output in tim2_ccer, or disable remap with tim2_or[4] select spi with sc1_mode select slave with sc1_spicfg select alternate output func tion with gpio_pbcfgl[7:4] sc1mosi o spi master data out of serial controller 1 either disable timer output in tim2_ccer, or disable remap with tim2_or[4] select spi with sc1_mode select master with sc1_spicfg select alternate output func tion with gpio_pbcfgl[7:4] sc1sda i/o twi data of serial controller 1 either disable timer output in tim2_ccer, ? or disable remap with tim2_or[4] select twi with sc1_mode select alternate open-drain output function with gpio_pbcfgl[7:4] sc1txd o uart transmit data of serial controller 1 either disable timer output in tim2_ccer, ? or disable remap with tim2_or[4] select uart with sc1_mode select alternate output func tion with gpio_pbcfgl[7:4] tim2c1 (see also pin 25) o timer 2 channel 1 output enable remap with tim2_or[4] enable timer output in tim2_ccer select alternate output function with gpio_pacfgl[7:4] tim2c1 (see also pin 25) i timer 2 channel 1 input disable remap with tim2_or[4] table 6.1. em359x pin descriptions (continued) pin # signal direction description note: 1. irqc and irqd external interrupts can be mapped to any digital i/o pin using the gpio_irqcsel and gpio_irqdsel registers. em359x 48 rev 1.0 38 pb2 i/o digital i/o sc1miso i spi master data in of serial controller 1 select spi with sc1_mode select master with sc1_spicfg sc1mosi i spi slave data in of serial controller 1 select spi with sc1_mode select slave with sc1_spicfg sc1scl i/o twi clock of serial controller 1 either disable timer output in tim2_ccer, ? or disable remap with tim2_or[5] select twi with sc1_mode select alternate open-drain output function with gpio_pbcfgl[11:8] sc1rxd i uart receive data of serial controller 1 select uart with sc1_mode tim2c2 (see also pin 29) o timer 2 channel 2 output enable remap with tim2_or[5] enable timer output in tim2_ccer select alternate output func tion with gpio_pbcfgl[11:8] tim2c2 (see also pin 29) i timer 2 channel 2 input enable remap with tim2_or[5] 39 swclk i/o serial wire clock input/output with debugger selected when in serial wire mode (see jtms description, pin 42) jtck i jtag clock input from debugger selected when in jtag mode (default mode, see jtms description, pin 42) internal pull-down is enabled table 6.1. em359x pin descriptions (continued) pin # signal direction description note: 1. irqc and irqd external interrupts can be mapped to any digital i/o pin using the gpio_irqcsel and gpio_irqdsel registers. em359x rev 1.0 49 40 pc2 i/o digital i/o enable with gpio_dbgcfg[5] and gpio_pccfgh[1] clear jtdo o jtag data out to debugger selected when in jtag mode (default mode, see jtms description, pin 42) swo o serial wire output asynchronous trace output to debugger select asynchronous trace interface in arm core enable trace interface in arm core select alternate output func tion with gpio_pccfgl[11:8] enable serial wire mode (see jtms description, pin 42) internal pull-up is enabled tracedata0 o synchronous cpu trace data bit 3 select 4-wire synchronous trace interface in arm core enable trace interface in arm core select alternate output func tion with gpio_pacfgl[11:8] 41 pc3 i/o digital i/o either enable with gpio_dbgcfg[5], ? or enable serial wire mode (see jtms description, pin 42) jtdi i jtag data in from debugger selected when in jtag mode (default mode, see jtms description, pin 42) internal pull-up is enabled traceclk o synchronous cpu trace clock enable trace interface in arm core select alternate output func tion with gpio_pccfgl[15:12] 42 pc4 i/o digital i/o enable with gpio_dbgcfg[5] jtms i jtag mode select from debugger selected when in jtag mode (default mode) jtag mode is enabled after pow er-up or by forcing nreset low select serial wire mode using the arm-defined protocol through a debug - ger internal pull-up is enabled swdio i/o serial wire bidirectional data to/from debugger enable serial wire mode (see jtms description) select serial wire mode using the arm-defined protocol through a debug - ger internal pull-up is enabled table 6.1. em359x pin descriptions (continued) pin # signal direction description note: 1. irqc and irqd external interrupts can be mapped to any digital i/o pin using the gpio_irqcsel and gpio_irqdsel registers. em359x 50 rev 1.0 43 pb0 i/o digital i/o vref analog o adc reference output enable analog function with gpio_pbcfgl[3:0] vref analog i adc reference input enable analog function with gpio_pbcfgl[3:0] enable reference output with an ember system function irqa i external interrupt source a tracedata2 (see also pin 30) o synchronous cpu trace data bit 2 select 4-wire synchronous trace interface in arm core enable trace interface in arm core select alternate output func tion with gpio_pbcfgl[3:0] tim1clk i timer 1 external clock input tim2msk i timer 2 external clock mask input 44 vdd_pads power pads supply (2.1?3.6 v) 45 pc1 i/o digital i/o adc3 analog adc input 3 enable analog function with gpio_pccfgl[7:4] tracedata3 (see also pin 31) o synchronous cpu trace data bit 3 select 1-, 2- or 4-wire synchronous trace interface in arm core enable trace interface in arm core select alternate output func tion with gpio_pccfgl[7:4] 46 vdd_mem power 1.8 v supply (flash, ram) 47 pc0 i/o high current digital i/o either enable with gpio_dbgcfg[5], ? or enable serial wire mode (see jtms description, pin 42) and disable tracedata1 jrst i jtag reset input from debugger selected when in jtag mode (default mode, see jtms description, ? pin 42) and tracedata1 is disabled internal pull-up is enabled irqd 1 i default external interrupt source d. tracedata1 o synchronous cpu trace data bit 1 select 2- or 4-wire synchronous trace interface in arm core enable trace interface in arm core select alternate output func tion with gpio_pccfgl[3:0] table 6.1. em359x pin descriptions (continued) pin # signal direction description note: 1. irqc and irqd external interrupts can be mapped to any digital i/o pin using the gpio_irqcsel and gpio_irqdsel registers. em359x rev 1.0 51 48 pb7 i/o high current digital i/o adc2 analog adc input 2 enable analog function with gpio_pbcfgh[15:12] irqc 1 i default external interrupt source c. tim1c2 o timer 1 channel 2 output enable timer output in tim1_ccer select alternate output func tion with gpio_pbcfgh[15:12] tim1c2 i timer 1 channel 2 input cannot be remapped 49 pe2 i/o digital i/o sc4scl i/o twi clock of serial controller 4 select twi with sc4_mode select alternate open-drain output function with gpio_pecfgl[11:8] sc4sclk o spi master clock of serial controller 4 enable master wi th sc4_spicfg[4] select spi with sc4_mode select alternate output func tion with gpio_pecfgl[11:8] sc4sclk i spi slave clock of serial controller 4 enable slave with sc4_spicfg[4] select spi with sc4_mode 50 pe3 i/o digital i/o sc4nssel i spi slave select of serial controller 4 enable slave with sc4_spicfg[4] select spi with sc4_mode table 6.1. em359x pin descriptions (continued) pin # signal direction description note: 1. irqc and irqd external interrupts can be mapped to any digital i/o pin using the gpio_irqcsel and gpio_irqdsel registers. em359x 52 rev 1.0 51 pb6 i/o high current digital i/o adc1 analog adc input 1 enable analog function with gpio_pbcfgh[11:8] irqb i external interrupt source b tim1c1 o timer 1 channel 1 output enable timer output in tim1_ccer select alternate output func tion with gpio_pbcfgh[11:8] tim1c1 i timer 1 channel 1 input cannot be remapped 52 pb5 i/o digital i/o adc0 analog adc input 0 enable analog function with gpio_pbcfgh[7:4] tim2clk i timer 2 external clock input tim1msk i timer 1 external clock mask input 53 vdd_core power 1.25 v digital core supply decoupling 54 vdd_pre power 1.8 v prescaler supply 55 vdd_synth power 1.8 v synthesizer supply 56 oscb i/o 24 mhz crystal oscillator or left open when using external clock input on osca 57 gnd ground ground supply pad in the bottom cent er of the package forms pin 57. see the various ember em359x reference design documentation for pcb con - siderations. table 6.1. em359x pin descriptions (continued) pin # signal direction description note: 1. irqc and irqd external interrupts can be mapped to any digital i/o pin using the gpio_irqcsel and gpio_irqdsel registers. em359x rev 1.0 53 6.1. packaging the em359x package is a plastic 56 -pin qfn that is 8 mm x 8 mm. figure 6.2 illustrates the package drawing. figure 6.2. package drawing em359x 54 rev 1.0 table 6.2. package dimensions dimension min nom max a 0.80 0.85 0.90 a1 0.00 0.02 0.05 a2 ? 0.65 0.67 a3 0.203 ref b 0.18 0.25 0.30 d 8.00 bsc e 0.50 bsc e 8.00 bsc j 5.95 6.02 6.15 k 5.95 6.02 6.15 l 0.35 0.40 0.45 aaa 0.1 bbb 0.1 ccc 0.08 ddd 0.1 eee 0.1 notes: 1. all dimensions shown are in millimeters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to the jedec solid state outline mo-220. 4. recommended card reflow profile is per the jedec/ipc ? j-std-020 specification for small body components. em359x rev 1.0 55 figure 6.3. solder mask dimensions em359x 56 rev 1.0 table 6.3. pcb land pattern dimension min c1 7.89 c2 7.89 e 0.50 x1 0.26 y1 0.84 x2 6.15 y2 6.15 notes: general 1. all dimensions shown are in m illimeters (mm) unless otherwise noted. 2. dimensioning and tolerancing is per the ansi y14.5m-1994 specification. 3. this land pattern design is based on the ipc-sm-782 guidelines. solder mask design 1. all pads are to be non-solder mask defined (nsmd). clear ance between the solder mask and the metal pad is to be 60 ? m minimum, all the way around the pad. card assembly 1. a no-clean, type-3 solder paste is recommended. 2. the recommended card reflow profile is per the jedec/ ipc j-std-020 specification for small body components. em359x rev 1.0 57 6.2. part marking figure 6.4 shows the part marking for the em359x series. the ci rcle in the top corner indicates pin 1. pins are numbered counter-clockwise from pin 1 with 14 pins per package edge. figure 6.4. part marking for em359x table 6.4. 56-pin qfn top marking explanation mark method: laser pin 1 marking: circle = 0.40 mm diameter (top-left justified) line 1 marking: device part number right justified em359x em359x is the orderable part number variant (EM3591/2/5/6/7/8) line 2 marking: tttttt = mfg code yy=year ww-work week manufacturing code from the assembly purchase form. assigned by the assembly house. corre - sponds to the year and work week. right justified line 3 marking: circle = 1.3 mm diameter center justified country of origin iso abbreviation right justified ?e3? indicates lead-free terminal finish tw em359x 58 rev 1.0 d ocument c hange l ist revision 0.1 ? initial draft revision 0.5 ? initial release revision 1.0 ? benchmark validation confirmed em359x rev 1.0 59 c ontact i nformation silicon laboratories inc. 400 west cesar chavez ? austin, tx 78701 please visit the silicon labs technical support web page: ? https://www.silabs.com/support/pages/contacttechnicalsupport.aspx ? and register to submit a technical support request. patent notice silicon labs invests in research and development to help our cust omers differentiate in the market with innovative low-power, s mall size, analog- intensive mixed-signal soluti ons. silicon labs' extensive pat ent portfolio is a testament to our unique approach and world-clas s engineering team. silicon laboratories and silicon labs are trademarks of silicon laboratories inc. other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. the information in this document is believed to be accurate in all respects at the time of publ ication but is subject to change without notice. silicon laboratories assumes no responsibili ty for errors and omissions, and disclaim s responsibility for any consequences resu lting from the use of information included herein. a dditionally, silicon laboratorie s assumes no responsibility for the functioning of und escribed fea- tures or parameters. silicon laboratories reserves the right to make changes without further notice. silicon laboratories makes no warran- ty, representation or guarantee regarding t he suitability of its products for any par ticular purpose, nor does silicon laborato ries assume any liability arising out of the application or use of any product or circuit, and specif ically disclaims any and all liability, in cluding without limitation consequential or incidental damages . silicon laboratories products are not designed, intended, or authorized for use in applica tions intend- ed to support or sustain life, or for any other application in which the failure of the silicon laboratories product could crea te a situation where personal injury or death may occur. should buyer purchase or us e silicon laboratories products for any such unintended or unaut horized application, buyer shall indemnify and hold silicon laboratories harmle ss against all claims and damages. |
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